1. Field of the Invention
The present invention relates generally to a DRAM memory cell and its manufacturing method and, more particularly, to a scalable stack-type DRAM memory structure and its manufacturing methods.
2. Description of Related Art
The dynamic-random-access memory (DRAM) cell including an access transistor and a storage capacitor has become the most important storage element in semiconductor industries, especially in computer and communication system. The memory density is increased very rapidly in order to decrease the cost per bit and, therefore, an advanced photolithography is in general needed to decrease the minimum-feature-size (F) of a cell.
In general, the output voltage of a DRAM memory cell is proportional to the capacitance value of the storage capacitor of the DRAM memory cell and, therefore, the storage capacitor must have a satisfactory capacitance value to have stable operation of the cell as the applied voltage is scaled. Basically, the storage capacitor can be implemented in a trench type or a stack type. The trench type is formed by forming a deep trench in a semiconductor substrate without increasing the surface area of the semiconductor-substrate surface; however, the deep-trench formation becomes very difficult as the minimum-feature-size is smaller than 0.15 xcexcm. The stack type is formed by implementing a capacitor structure over the access transistor and its nearby dummy-transistor structure through the conductive contact-plug over the node diffusion region of the access transistor; however, the finite surface area over the access transistor becomes very difficult for forming a complicate capacitor structure as the minimum-feature-size is smaller than 0.15 xcexcm. Accordingly, the limit cell size of the stack type is 8F2 for shallow-trench-isolation and, in general, the practical cell size is between 8F2 and 12F2. The limit cell size of the trench type is 6F2 for the excess transistor being formed over the semiconductor surface and, in general, the practical cell size is between 6F2 and 10F2.
A typical example of a stack-type DRAM memory is shown in FIG. 1, in which a pair of transistor-stacks 26 are formed over an active region including a common-drain diffusion region 27 and two common-source diffusion regions 25, 29, and a pair of dummy-transistors 24 are formed over the field-oxide layers 14 surrounding the active region. It is clearly seen that the alignment of the two dummy-transistors 24 to the edges of the active region is critical, the lateral dimension of the cell should be larger than 4F; the alignment of the bit-line contact 55 to the common-drain diffusion region 27 between a pair of sidewall dielectric spacers 30 is also critical, the space between two transistor-stacks needs to be larger than 1F; Similarly, the alignment of the node contact 54 is critical too, the space between the transistor-stack 26 and the dummy-transistor 24 needs to be larger than 1F. As a consequence, the cell size of FIG. 1 would be larger than 10F2 for isolation using local-oxidation of silicon (LOCOS), and these basic disadvantages can be easily found from most of the DRAM structure of the prior art, for examples: U.S. Pat. No. 6,297,525 B1, U.S. Pat. No. 6,329,684 B1, and U.S. Pat. No. 6,352,896 B1.
It is, therefore, a major objective of the present invention to offer a scalable stack-type DRAM memory structure without a dummy-transistor structure for obtaining a scalable cell size smaller than 6F2.
It is another objective of the present invention to offer a high-capacity DRAM capacitor structure without using a larger semiconductor surface area.
It is a further objective of the present invention to offer a contactless memory structure including both bit-line nodes and capacitor nodes to alleviate the scaling effects.
Accordingly, the present invention discloses a scalable stack-type DRAM memory structure and its manufacturing methods. The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure of the present invention comprises a plurality of transistor-stacks being formed transversely to the plurality of STI regions and over a shallow-trench-isolation (STI) structure having a plurality of STI regions and a plurality of active regions formed alternately on a semiconductor substrate of a first conductivity type, wherein each of the plurality of transistor-stacks being formed by a spacer-formation technique comprises an elongated second conductive layer being formed over a flat surface alternately formed by a first conductive layer over a gate-dielectric layer in each of the plurality of active regions and a first raised field-oxide layer in each of the plurality of STI regions, a capping-dielectric layer being formed on the elongated second conductive layer, and a masking sidewall dielectric spacer being formed over the capping-dielectric layer; a plurality of common-source regions and a plurality of common-drain regions being formed alternately and transversely to the plurality of STI regions, wherein each of the plurality of common-source regions comprises two source regions separated by a self-aligned STI region being formed by another spacer-formation technique. Each of the plurality of common-drain regions being scalable comprises a second flat bed being formed alternately by a third raised field-oxide layer and a common-drain diffusion region of a second conductivity type, a plurality of planarized third conductive islands being formed between a pair of composite first sidewall dielectric spacers and on the common-drain diffusion regions, a first buffer-dielectric layer being formed over one sidewall of each of the plurality of transistor-stacks with a portion under each of a pair of first sidewall dielectric spacers, and a second planarized dielectric layer being formed between the planarized third conductive islands, wherein the common-drain diffusion region comprises a lightly-doped common-drain diffusion region being formed by implanting doping impurities across the first buffer-dielectric layer outside of first sidewall buffer-dielectric layers in a self-aligned manner and a shallow heavily-doped common-drain diffusion region being formed by implanting doping impurities in a self-aligned manner across the first buffer-dielectric layer outside of the pair of first sidewall dielectric spacers. The source region comprises a first flat bed being formed alternately by a third raised field-oxide layer and a source diffusion region of the second conductivity type, a second buffer-dielectric layer being formed over another sidewall of each of the plurality of transistor-stacks with a portion under each of a pair of second sidewall dielectric spacers, a thin fourth conductive island being formed over the source diffusion region between a composite second sidewall dielectric spacer and the first planarized dielectric layer being formed over said self-aligned STI region; and a third sidewall dielectric-spacer island being formed over each of the thin third conductive islands and between two second planarized dielectric layers formed over nearby STI regions, wherein the source diffusion region comprises a lightly-doped source diffusion region being formed by implanting doping impurities across the second buffer-dielectric layer outside of the second sidewall buffer-dielectric layer in a self-aligned manner and a shallow heavily-doped source diffusion region being formed by implanting doping impurities in a self-aligned manner across the second buffer-dielectric layer outside of the second sidewall dielectric spacer.
The DRAM capacitor structure of the present invention comprises a plurality of rectangular tube-shaped cavities being formed over the thin fourth conductive islands and a plurality of bit lines being integrated with the planarized third conductive islands through a plurality of planarized conductive contact-islands for forming a contactless bit-line node structure.
For a first-type DRAM capacitor structure, a first side of the rectangular tube-shaped cavity is formed by a composite first sidewall dielectric spacer, a second side being an opposite side of the first side is formed by a first planarized dielectric layer in the self-aligned STI region, and a third side and a fourth side are separately formed by a second planarized dielectric layer in the STI region. A fifth conductive layer is formed over an inner sidewall of the rectangular-tube-shaped cavity together the thin fourth conductive island being acted as a source plate, a capacitor-dielectric layer is formed at least over the source plate, and a sixth conductive layer or a planarized sixth conductive layer is formed over the capacitor-dielectric layer to act as a ground plate for forming a high-capacity DRAM capacitor structure.
For a second-type DRAM capacitor structure of the present invention, a first side of the rectangular tube-shaped cavity is formed by a composite first sidewall dielectric spacer and a first interlayer-conductive island over a first interlayer-dielectric island being formed on the nearby transistor-stack and a portion of the composite first sidewall dielectric spacer, a second side being an opposite side of the first side is formed by a third planarized dielectric layer over a first planarized dielectric layer in the self-aligned STI region, and a third side and a fourth side are separately formed by a fourth planarized dielectric layer over a second planarized dielectric layer in the STI region. A fifth conductive layer is formed over an inner sidewall of the rectangular tube-shaped cavity and an outer sidewall of the first interlayer-conductive island over a first interlayer-dielectric island together with the thin fourth conductive island being acted as a source plate, a capacitor-dielectric layer is formed at least over the source plate, and a sixth conductive layer or a planarized sixth conductive layer is formed over the capacitor-dielectric layer to act as a ground plate for forming a high-capacity DRAM capacitor structure.
The cell size of the DRAM memory structure as described is scalable and can be made to be smaller than 6F2 and the DRAM capacitor structure may offer a larger surface area for forming a high-capacity DRAM capacitor.